FPGA are one of the most cost efficient alternatives for SoC implementation, specially those that are based in SW cores processors, but it doesn’t exist nowadays any tool with features similar to ours. Our solution offers a simulation speed more than 2•103 higher than the commercial options already in the market. In addition the former only allow to evaluate design performance by means of trial and error approach, being an extremely inefficient alternative.
Description of the technology
A research group from the Electronic Department of Alcalá University has developed a technology for the designing and verification of System on Chip (SoC). These tools allow to simulate at high speed, the SoC behaviour in its double aspect HW/SW, providing to the designer a rapid and precise information about the performance of the evaluated design. This allows to reduce the development time and consequently the time-to-market. The group looks for companies from aerospace and ICT sector to sign commercial agreements with technical assistance.
Specifications
System On Chip technologies are especially useful in aerospace applications like avionics systems, missiles, unmanned vehicles and smart munitions, where high performance processing systems with high power efficiency are required and limited space for electronic systems is a common constraint. The tools developed by the group allow: - joint verification of both hardware and software of the SoC, - starting the development of the embedded software without needing to have the real platform, - detecting in a rapid and precise way functional errors and/or design bottlenecks, - evaluating different architectural alternatives and - carrying out a quantitative analysis of each alternative in order to determine the optimum architecture of the SoC, etc. An integrated environment is arranged that has the necessary tools to cover the different phases of the SoC development and verification flow: - A processor simulator based on binary translation techniques for embedded software development and debugging. - HW/SW co-simulation environment based on models TLM for design space exploration. - Analysis tools. They allow to obtain quantitative performance information about the processor (classic profiling, gantt charts), memory subsystem memory (cache hit rate, average access latency, data access traces) and bus architecture (occupation level, effective bus bandwidth, average arbitration time), etc. - RTL HW/SW co-simulation environment for the verification of the final design implementation.
Main advantages of its use
Applications
Additional information (attached documents)
The Technology Transfer Office at Alcalá University serves as a liaison between the University and its socioeconomic environment in terms of research and innovation. It encorages collaboration between research groups from universities and companies/institutions, with the objective to promote and commercialize research results and scientific capabilities.
Some of the services offered by this office are specified in the following list:
- Promotion of R & D and improvement of the relationships with companies.
- Promote the participation in R & D projects applicants to public calls (regional, national and European).
- Advising, processing and monitoring of patents and other forms of industrial protection.
- Support in the negotiation of contracts and agreements for R&D&i
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